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Accelerating Test, Validation and Debug of High Speed Serial Interfaces
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  • English
  • Year: 2011
  • Author: Yongquan Fan, Zeljko Zilic (auth.)
Accelerating Test, Validation and Debug of High Speed Serial Interfaces
  • PDF
  • English
  • Year: 2011
  • Author: Yongquan Fan, Zeljko Zilic (auth.)
Verification by Error Modeling: Using Testing Techniques in Hardware Verification
  • PDF
  • English
  • Year: 2004
  • Author: Katarzyna Radecka, Zeljko Zilic (auth.)
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
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  • English
  • Year: 2008
  • Author: Dr. Marc Boulé, Professor Zeljko Zilic (auth.)
Accelerating test, validation and debug of high speed serial interfaces
  • PDF
  • English
  • Year: 2010;2011
  • Author: Fan, Yongquan;Fan, Yongquan
Verification by error modeling : using testing techniques in hardware verification
  • PDF
  • English
  • Year: 2003
  • Author: Katarzyna Radecka; Zeljko Zilic
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
  • PDF
  • English
  • Year: 2008
  • Author: Marc Boulé, Zeljko Zilic
Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
  • PDF
  • English
  • Year: 2003
  • Author: Katarzyna Radecka, Zeljko Zilic
Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
  • PDF
  • English
  • Year: 2003
  • Author: Katarzyna Radecka, Zeljko Zilic
Generating hardware assertion checkers: for hardware verification, emulation, post-fabrication debugging and on-line monitoring
  • PDF
  • English
  • Year: 2008
  • Author: Marc Boulé, Zeljko Zilic
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