Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
- Author
- Katarzyna Radecka, Zeljko Zilic
- Language
- English
- Edition
- 1
- Year
- 2003
- Page
- 233
- ISBN
- 1402076525,9781402076527,9780306487392
- File Type
- pdf
- File Size
- 13.8 MiB
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