Verification by Error Modeling: Using Testing Techniques in Hardware Verification
- Author
- Katarzyna Radecka, Zeljko Zilic (auth.)
- Publisher
- Springer US
- Language
- English
- Edition
- 1
- Year
- 2004
- Page
- 216
- ISBN
- 978-1-4020-7652-7,978-0-306-48739-2
- File Type
- pdf
- File Size
- 13.7 MiB
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