Home Advanced Search

Advanced Search - Page 1

Design Automation for Timing-Driven Layout Synthesis
  • PDF
  • English
  • Year: 1993
  • Author: Sachin S. Sapatnekar, Sung-Mo Kang (auth.)
Timing
  • PDF
  • English
  • Year: 2004
  • Author: Sachin S Sapatnekar
Timing Analysis and Optimization of Sequential Circuits
  • PDF
  • English
  • Year: 1999
  • Author: Naresh Maheshwari, Sachin S. Sapatnekar (auth.)
Electromigration Inside Logic Cells: Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS
  • PDF
  • English
  • Year: 2017
  • Author: Gracieli Posser, Sachin S. Sapatnekar, Ricardo Reis (auth.)
Hot-Carrier Reliability of MOS VLSI Circuits
  • PDF
  • English
  • Year: 1993
  • Author: Yusuf Leblebici, Sung-Mo (Steve) Kang (auth.)
Modeling of Electrical Overstress in Integrated Circuits
  • PDF
  • English
  • Year: 1995
  • Author: Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury (auth.)
Timing
  • PDF
  • English
  • Year: 2004
  • Author: Sachin Sapatnekar
Timing
  • PDF
  • English
  • Year: 2010
  • Author: Sachin Sapatnekar
Designing Digital Computer Systems with Verilog
  • PDF
  • English
  • Year: 2005
  • Author: David J. Lilja, Sachin S. Sapatnekar
CMOS Digital Integrated Circuits Analysis & Design
  • PDF
  • English
  • Year: 2003
  • Author: Sung-Mo (Steve) Kang, Yusuf Leblebici
search