Formal Semantics and Proof Techniques for Optimizing VHDL Models

Formal Semantics and Proof Techniques for Optimizing VHDL Models

Author
Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey (auth.)
Publisher
Springer US
Language
English
Edition
1
Year
1999
Page
158
ISBN
978-1-4613-7331-5,978-1-4615-5123-2
File Type
pdf
File Size
12.2 MiB

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